MOS Technology 6502 Instruction Set (inclusing 65C02 extensions) author Neil Franklin, last modification 2020.02.17 Sources for this data: ---------------------- 1. List of instruction mnemonics and opcodes and byte lengths (but not flags), in format like the "by opcode number" table below. Assembled manually from data in borrowed library book "Programming the 6502" by Rodney Zaks, from sometime mid 1980s. Used that for programming Commodore 64 (second computer I owned, third I programmed) for years, so it can be assumed to be correct. 2. Page condensing above list and adding reconstruction of flags from memory, in format like the "instruction code table" at the bottom. That was used when writing an 6502 emulator, which was capable of running an existing 16k 6502 program (Commodore 64 Operating System), so it can also be assumed to be correct. (BTW: This file started its life as an attempt to digitalise that page, and snowballed after that, which also included adding all the many other processors instruction set files in this directory, becoming an entire documentation set!) 3. Source code of above mentioned running 6502 emulator, available at: http://neil.franklin.ch/Projects/Soft64/ in particular the actual CPU at: http://neil.franklin.ch/Projects/Soft64/Soft64View.m in mpu_64us(). 4. Later crosschecked with official MCS6500 Microcomputer Family Programming Manual, January 1976, Second Edition, Revision A, from: http://www.bitsavers.org/components/mosTechnology/6500-50A_MCS6500pgmManJan76.pdf 5. Even later added 65C02 extensions in official WDC 65C02 manual, from: http://www.westerndesigncenter.com/wdc/documentation/w65c02s.pdf Of course errors of my own are to be expected. Registers: ---------- (in order: data, address, pc, flags) A 8bit Accumulator X Y 8bit Index Registers (00:XX or 00:YY merged as high,low addr) S 8bit Stack Pointer (01:SS merged as high,low address) (push post-decr(!), pull pre-incr(!)) PC 16bit Program Counter P 8bit Processor Status Register (= flags) Processor Status Register, Flags: --------------------------------- (in order: from MSB/7 to LSB/0) bit 76543210 flag NV1BDIZC N Negative result (result bit7 set) V oVerflow (arithmetic result carry bit6->bit7 XOR bit7->"bit8") 1 expansion (always 1) B Break (1 after BRK, 0 after IRQ, only on stack) D Decimal mode (1 makes ADC/SBC decimal, 0 binary, INC/DEC always binary) I Interupt disable (1 disables IRQ) Z Zero result (result with all bits cleared) C Carry (arithmetic result carry bit7->"bit8") General policy seems to be, by category: - arithmetic: set all NVZC (except compares only NZC) - decrement/increment: set NZ, leave VC unchanged, so address inc/dec leaves VC - logic stuff and load: set NZ (except bit test special NV behaviour (= bit76)) - store: leave all flags (exept TXA/TYA despite STX/STY A pretend to be loads) - shift/rotate: set NZC - jump/branch/call/return: leave all flags unchanged General policy seems to be, by flag: - Flag V: arithmetic (exept compares), but BIT special behaviour - Flag C: arithmetic (including compares), shift/rotate - Flag Z: arithmetic (i), sh/rot, dec/inc, load, transf (exept TXS), logic, BIT - Flag N: same as Z, except BIT special behaviour Memory: ------- Program+Data memory 64k*8bit (16bit address space) (I/O uses part of above, memory mapped I/O (section of address space)) Addressing Modes, in Assembler Syntax: -------------------------------------- (in order: register, immediate, address, reg indexed, mem indir, pc) A accumulator X Y index register S stack pointer register #ii immediate8 (2 hex digits) zz address8 (in zero page, gives 00zz) hhll address16 -nameless- stack pointer indirect decrement/increment (only PH*/PL* instr) zz,X zz,Y address8 + X or Y index register (0..255) (zz,Y only LDX/STX) hhll,X hhll,Y address16 + X or X index register (0..255) (zz) address8 (in zp) indirect, no index (only in 65C02) (zz,X) address8 (in zp) + X register preindex, then indirect (zz),Y address8 (in zp) indirect, then + Y register postindex (hhll) address16 indirect (only JMP () instr, should be JIN hhll) rr PC + offset8 (-128..+127) (only Bcc instr) Instruction Formats, in Machine Code Bytes: ------------------------------------------- (in order: simple, immediate, memory, jump, conditional) oooooooo opcode8 ooommmoo iiiiiiii opcode5+mode3 immed8 (arithmetic/logic immed) ooommmoo zzzzzzzz opcode5+mode3 zp-addr8 (arithmetic/logic) ooommmoo llllllll hhhhhhhh opcode5+mode3 addr-low8 addr-high8 (arith/logic) oooooooo llllllll hhhhhhhh opcode8 addr-low8 addr-high8 (jump/subroutine) cccooooo rrrrrrrr opcode5+cond3 offset8 (branch) fffooooo opcode5+flag3 (flag) Instruction Bit Patterns and Operations: ---------------------------------------- (in order: functional grouping: data transfer, arithmetic, jumps, auxillary) load/store and arithmetic/logic A ooommm01 ooo..... opcode operation 000..... ORA A = A bitwise-OR mem[address]; FlagsNZ "OR Accumulator" 001..... AND A = A bitwise-AND mem[address]; FlagsNZ "AND" 010..... EOR A = A bitwise-excl-OR mem[address]; FlagsNZ "Exclusive OR" 011..... ADC A = A + mem[address] + FlagC; FlagsNVZC "ADd with Carry" (for ADD FlagC must be cleared with CLC, as 1 = carry +1) 100..... STA mem[address] = A; Flags -none- (store) "STore Accumulator" 101..... LDA A = mem[address]; FlagsNZ "LoaD Accumulator" 110..... CMP discard A - mem[address]; FlagsNZC(noV!) "CoMPare" 111..... SBC A = A - mem[address] - NOT FlagC; FlagsNVZC "SuBtr w Carry" (for SUB FlagC must be set with SEC, as 0 = borrow -1) ...mmm.. mode address ...000.. (zz,X) mem[mem[PC+]+X] (address8 zeropage +preindex, indirect16) (next to useless, (zz),X or (zz,S) would be better) ...001.. zz mem[PC+] (address8 zeropage) ...010.. #ii PC+ (immediate8) (not with STA, is modify immediate, senseless) ...011.. hhll mem[PC++] (address16 absolute) ...100.. (zz),Y mem[mem[PC+]]+Y (address8 zeropage, indirec16 +postindex) ...101.. zz,X mem[PC+]+X (address8 zeropage +index) ...110.. hhll,Y mem[PC++]+Y (address16 absolute +index) ...111.. hhll,X mem[PC++]+X (address16 absolute +index) load/store and arithmetic/logic A (additional modes) ooommm10 (only in 65C02) ooo..... opcode operation (same as above) ...mmm.. mode address ...100.. (zz) mem[mem[PC+]] (address8 zeropage, indirec16 no index) load/store X/Y and shift/rotate and increment/decrement and bit test ooommmo0 ooo..... opcode operation 000...1. ASL FlagC,mem[address] = mem[address],0; FlagsNZC "Arithmetic Shift Left" 001...0. BIT FlagsNV = bit76(mem[address]) FlagZ = A bitwise-AND mem[address]; FlagsNVZ "BIt Test" (combines 6800 TST in FlagsNV and 6800 BIT in FlagZ) 001...1. ROL FlagC,mem[address] = mem[address],FlagC; FlagsNZC "ROtate Left" 010...1. LSR mem[address],FlagC = 0,mem[address]; FlagsNZC "Logical Shift Right" 011...1. ROR mem[address],FlagC = FlagC,mem[address]; FlagsNZC "ROtate Right" 100...0. STY mem[address] = Y; Flags -none- (store) "STore Y register" ...1100. TYA A = Y (actually STY A); FlagsNZ (despite is store!) "Transfer Y register to Accumulator" 100...1. STX mem[address] = X; Flags -none- (store) "STore X register" ...0101. TXA A = X (actually STX A); FlagsNZ (despite is store!) "Transfer X register to Accumulator" ...1101. TXS S = X (actually STX S); Flags -none- (despite TXA has!) "Transfer X register to Stack pointer" 101...0. LDY Y = mem[address]; FlagsNZ "LoaD Y register" ...0100. TAY Y = A (actually LDY A); FlagsNZ "Transfer Accumulator to Y register" 101...1. LDX X = mem[address]; FlagsNZ "LoaD X register" ...0101. TAX X = A (actually LDX A); FlagsNZ "Transfer Accumulator to X register" ...1101. TSX X = S (actually LDX S); FlagsNZ "Transfer Stack pointer to X register" 110...0. CPY discard Y - mem[address]; FlagsNZC "ComPare Y register" 110...1. DEC mem[address] = mem[address] - 1; FlagsNZ(noC!) "DECrement" 111...0. CPX discard X - mem[address]; FlagsNZC "ComPare X register" 111...1. INC mem[address] = mem[address] + 1; FlagsNZ(noC!) "INCrement" ...mmm.. mode address ...000.. #ii PC+ (immediate8) (instead of (zz,X)) (only for LDY/LDX/CPY/CPX) (with STY/STX is modify immediate, senseless) (same also for shift/rotate and increment/decrement) (not with BIT, which collides with missplaced JSR(!)) ...001.. zz mem[PC+] (address8 zeropage) ...010.. A A (instead of # (immediate8) which got moved) (not for DEC (DEX is there!) and INC (NOP is there!)) (is for TAY/TXA/TAX, but not for TYA (DEY is there!)) ...011.. hhll mem[PC++] (address16 absolute) ...100.. - not used for this group (are Bcc, and 65C02 all (zz)) ...101.. zz,X mem[PC+]+X (address8 zeropage +index) (for STX/LDX changed to zz,Y to be more usefull) (not for BIT and CPY/CPX, are missing, why?) ...110.. S or A S or A (instead of hhll,X) (S only for TSX = LDX S and TXS = STX S) (A only for TYA (this opcode would be SEV!)) ...111.. hhll,X mem[PC++]+X (address16 absolute +index) (for LDX (no STX) changed to hhll,Y to be more usefull) (not for BIT CPY/CPX and STY/STX, are missing, why?) bit test and set/reset oooommo0 (only in 65C02) oooo..o. opcode operation 0000..0. TSB mem[address] = A bitwise-OR mem[address] FlagZ = A bitwise-AND mem[address]; FlagZ "Test Set Bit" 0001..0. TRB mem[address] = not-A bitwise-AND mem[address] FlagZ = A bitwise-AND mem[address]; FlagZ "Test Reset Bit" ....mm.. mode address ....01.. zz mem[PC+] (address8 zeropage) ....11.. hhll mem[PC++] (address16 absolute) bit test (additional modes) ooommmo0 (only in 65C02) 001...0. BIT FlagsNV = bit76(mem[address]) FlagZ = A bitwise-AND mem[address]; FlagsNVZ "BIt Test" ...101.. zz,X mem[PC+]+X (address8 zeropage +index) (missing mode got added back in) ...111.. hhll,X mem[PC++]+X (address16 absolute +index) (missing mode got added back in) bit test (additional mode) ooommm01 (only in 65C02) ooo..... opcode operation 100..... BIT FlagsNV = bit76(mem[address]) FlagZ = A bitwise-AND mem[address]; FlagsNVZ "BIt Test" ...mmm.. mode address ...010.. #ii PC+ (immediate8) (takes place of STA #ii, as that was senseless) store zero ooommmo0 (only in 65C02) ooo..... opcode operation 011...0. STZ mem[address] = 0; Flags -none- (store) "STore Zero" ...mmm.. mode address ...001.. zz mem[PC+] (address8 zeropage) ...101.. zz,X mem[PC+]+X (address8 zeropage +index) store zero (additional modes) oooooom0 (only in 65C02) oooooo.. opcode operation 100111.. STZ mem[address] = 0; Flags -none- (store) "STore Zero" ......m. mode address ......0. hhll mem[PC++] (address16 absolute +index) ......1. hhll,X mem[PC++]+X (address16 absolute +index) increment/decrement (additional modes) ooommmo0 (only in 65C02) ooo...o. opcode operation 000...1. INC mem[address] = mem[address] + 1; FlagsNZ(noC!) "INCrement" 001...1. DEC mem[address] = mem[address] - 1; FlagsNZ(noC!) "DECrement" ...mmm.. mode address ...110.. A A (instead of hhll,X) (take place of ASL/TOL S, as that was senseless)) increment/decrement X/Y 1oo010o0 .oo...o. opcode operation .00...0. DEY Y = Y - 1; FlagsNZ(noC!) (opcode would be STY A!) "DEcrement Y register" .10...0. INY Y = Y + 1; FlagsNZ(noC!) (opcode would be CPY A!) "INcrement Y register" .10...1. DEX X = X - 1; FlagsNZ(noC!) (opcode would be DEC A!) "DEcrement X register" .11...0. INX X = X + 1; FlagsNZ(noC!) (opcode would be CPX A!) "INcrement X register" stack push/pull 0ro01000 .ro..... opcode operation (push post-decr(!), pull pre-incr(!)) .00..... PHP mem[01:SS-] = P "PusH Processor status register" .01..... PLP P = mem[01,+SS]; Flags -all- "PulL Processor stat register" .10..... PHA mem[01:SS-] = A "PusH Accumulator" .11..... PLA A = mem[01,+SS]; FlagsNZ "PulL Accumulator" stack push/pull (additional registers) r1o11010 (only in 65C02) r.o..... opcode operation (push post-decr(!), pull pre-incr(!)) 0.0..... PHY mem[01:SS-] = Y "PusH index Y" 0.1..... PLY Y = mem[01,+SS]; FlagsNZ "PulL index Y" 1.0..... PHX mem[01:SS-] = X "PusH index X" 1.1..... PLX X = mem[01,+SS]; FlagsNZ "PulL index X" jumps/subroutines and reset/interrupts oooooooo opcode operation (push post-decr(!), pull pre-incr(!)) 00000000 BRK mem[01:SS---] = PC+1(!),P; FlagB=1; FlagI=1 PC = mem[FFFE/FFFF] (as IRQ, just FlagB=1) "BReaK" if BRK ends with RTI, the former becomes 2-byte 00100000 JSR hhll mem[01:SS--] = PC-1(!); PC = mem[PC++] (address16) "Jump SubRoutine" 01000000 RTI P,PC = mem[01:+++SS]; Flags -all- "ReTurn fr Interrupt" 01001100 JMP hhll PC = mem[PC++] (address16) "JuMP" 01100000 RTS PC = mem[01:++SS]+1(!) "ReTurn from Subroutine" 01101100 JMP (hhll) PC = mem[mem[PC++]] (address16, indirect16) "JuMP" if [mem[PC++] is hhFF, then the indirect addresses hh part comes from hh00, not (hh+1)00, this is a bug in the processor, it forgets to take over the carry (this has been corrected in 65C02) 01111100 JMP(hhll,X) PC = mem[mem[PC++]+X] (address16, indirect16) "JuMP" (only in 65C02) 10000000 BRA rr PC = PC+mem[PC+] (offset8) "BRanch Allways" 11101010 NOP do nothing (opcode would be INC A!) "No OPeration" ---- pin RESET non-write mem[01:SS---] = PC,P; FlagI=1; PC = mem[FFFC/FFFD] "RESET" ---- pin NMI mem[01:SS---] = PC,P; FlagI=1 PC = mem[FFFA/FFFB] "Non Maskable Interrupt" ---- pin IRQ mem[01:SS---] = PC,P; FlagB=0; FlagI=1 PC = mem[FFFE/FFFF] (as BRK, just FlagB=0) "Interrupt ReQuest" ---- pin SEV FlagV=1 (for spinloop CLV; BVC -2) "SEt V flag" branches/conditionals cccooooo opcode operation ...ooooo ...10000 Bcc rr if condition then PC = PC+mem[PC+] (offset8) "Branch cc" ccc..... cc condition 000..... PL N = 0 "PLus" 001..... MI N = 1 "MInus" 010..... VC V = 0 "oVerflow Clear" 011..... VS V = 1 "oVerflow Set" 100..... CC C = 0 "Carry Clear" 101..... CS C = 1 "Carry Set" 110..... NE Z = 0 "Not Equal" 111..... EQ Z = 1 "Equal" flags ffo11000 ff...... f flag 00...... C Carry 01...... I Interrupt 10...... V oVerflow 11...... D Decimal1 ..o..... opcode operation ..0..... CLf Flagf = 0 (not for CLV, as TYA is there!) "CLear flag" ..1..... SEf Flagf = 1 (no SEV, reused for CLV, FlagV=0!) "SEt flag" Instruction Code List: ---------------------- (full machine code bytes, in order: opcode number) 00 BRK 10rr BPL rr 20llhh JSR hhll 30rr BMI rr 01zz ORA (zz,X) 11zz ORA (zz),Y 21zz AND (zz,X) 31zz AND (zz),Y -- - 12zz ora (zz) -- - 32zz and (zz) -- - -- - -- - -- - 04zz tsb zz 14zz trb zz 24zz BIT zz 34zz bit zz,X 05zz ORA zz 15zz ORA zz,X 25zz AND zz 35zz AND zz,X 06zz ASL zz 16zz ASL zz,X 26zz ROL zz 36zz ROL zz,X -- -- -- - -- - -- - 08 PHP 18 CLC 28 PLP 38 SEC 09ii ORA #ii 19llhh ORA hhll,Y 29ii AND #ii 39llhh AND hhll,Y 0A ASL A 1A inc a 2A ROL A 3A dec a -- - -- - -- - -- - 0Cllhh tsb hhll 1Cllhh trb hhll 2Cllhh BIT hhll 3Cllhh bit hhll,X 0Dllhh ORA hhll 1Dllhh ORA hhll,X 2Dllhh AND hhll 3Dllhh AND hhll,X 0Ellhh ASL hhll 1Ellhh ASL hhll,X 2Ellhh ROL hhll 3Ellhh ROL hhll,X -- - -- - -- - -- - 04|0C|12|14|1A|1C|32|34|3A|3C in lowercase are 65C02 extensions 02|22: these two and also 42|62 are said by one source to crash the processor loop internally, claim even RESET will not work, need power off/on to restart but other source says this applies all codes with x2, except A2 (LDX #) and while IRQ and even NMI will not work, as looping, RESET will break loop 04|0C|14|1C would better fit JSR instead of 20, with all of zz zz,X hhll hhll,X is for internal optimisation, can only load one temp register with low addr then push PC to stack after 2nd byte of 3, then only load high addr 3rd byte because of this RTS pulls PC from stack and then must increment it before use for JSR+RTS only 6+6=12clk instead of 6800 9+5=14clk, save 2/14, 14% faster 20: would be BIT #ii ; but used for above JSR hhll 34: would be BIT zz,X ; unused, missing for unknown reasons, is in 65C02 3C: would be BIT hhll,X ; unused, missing for unknown reasons, is in 65C02 40 RTI 50rr BVC rr 60 RTS 70rr BVS rr 41zz EOR (zz,X) 51zz EOR (zz),Y 61zz ADC (zz,X) 71zz ADC (zz),Y -- - 52zz eor (zz) -- - 72zz adc (zz) -- - -- - -- - -- - -- - -- - 64zz stz zz 74zz stz zz,X 45zz EOR zz 55zz EOR zz,X 65zz ADC zz 75zz ADC zz,X 46zz LSR zz 56zz LSR zz,X 66zz ROR zz 76zz ROR zz,X -- - -- - -- - -- - 48 PHA 58 CLI 68 PLA 78 SEI 49ii EOR #ii 59llhh EOR hhll,Y 69ii ADC #ii 79llhh ADC hhll,Y 4A LSR A 5A phy 6A ROR A 7A ply -- -- - -- - -- - 4Cllhh JMP hhll -- - 6Cllhh JMP (hhll) 7Cllhh jmp (hhll,X) 4Dllhh EOR hhll 5Dllhh EOR hhll,X 6Dllhh ADC hhll 7Dllhh ADC hhll,X 4Ellhh LSR hhll 5Ellhh LSR hhll,X 6Ellhh ROR hhll 7Ellhh ROR hhll,X -- - -- - -- - -- - 52|5A|64|72|74|7A|7C in lowercase are 65C02 extensions 44: would be JMP zz ; unused, missing for unknown reasons 54: would be JMP zz,X ; unused, missing for unknown reasons 5C: would be JMP hhll,X ; unused, missing for unknown reasons 64: would be JMP (zz) ; unused, missing for unknown reasons 6C: if instr is 6CFFhh then the indirect addr hh comes from hh00, not (hh+1)00 this is a bug in the processor, it forgets to take over the carry this has been corrected in the CMOS 65C02 version 74: would be JMP (zz,X) ; unused, missing for unknown reasons 7C: would be JMP (hhll,X) ; unused, missing for unknown reasons, is in 65C02 80rr bra rr 90rr BCC rr A0ii LDY #ii B0rr BCS rr 81zz STA (zz,X) 91zz STA (zz),Y A1zz LDA (zz,X) B1zz LDA (zz),Y --ii --- #ii 92zz sta (zz) A2ii LDX #ii B2zz lda (zz) -- - -- - -- - -- - 84zz STY zz 94zz STY zz,X A4zz LDY zz B4zz LDY zz,X 85zz STA zz 95zz STA zz,X A5zz LDA zz B5zz LDA zz,X 86zz STX zz 96zz STX zz,Y A6zz LDX zz B6zz LDX zz,Y -- - -- - -- - -- - 88 DEY 98 TYA A8 TAY B8 CLV 89ii bit #ii 99llhh STA hhll,Y A9ii LDA #ii B9llhh LDA hhll,Y 8A TXA 9A TXS AA TAX BA TSX -- - -- - -- - -- - 8Cllhh STY hhll 9Cllhh stz hhll ACllhh LDY hhll BCllhh LDY hhll,X 8Dllhh STA hhll 9Dllhh STA hhll,X ADllhh LDA hhll BDllhh LDA hhll,X 8Ellhh STX hhll 9Ellhh stz hhll,X AEllhh LDX hhll BEllhh LDX hhll,Y -- - -- - -- - -- - 80|89|92|9C|9E|B2 in lowercase are 65C02 extensions 80: would be STY #ii ; is modify immediate, senseless, so no opcode, C02 BRA 82: would be STX #ii ; is modify immediate, senseless, so no opcode 88: would be STY A ; but is used for DEY 89: would be STA #ii ; is modify immediate, senseless, so no opcode, C02 BIT 96: would be STX zz,X ; but is changed to STX zz,Y to be more usefull 98: would be SEV ; but is used for TYA (= STY A), would better fit at 88 9E: would be STY hhll,X ; unused, missing for unknown reasons 9E: would be STX hhll,X ; unused, missing unknown, change hhll,Y more usefull B6: would be LDX zz,X ; but is changed to LDX zz,Y to be more usefull BE: would be LDX hhll,X ; but is changed to LDX hhll,Y to be more usefull C0ii CPY #ii D0rr BNE rr E0ii CPX #ii F0rr BEQ rr C1zz CMP (zz,X) D1zz CMP (zz),Y E1zz SBC (zz,X) F1zz SBC (zz),Y -- - D2zz cmp (zz) -- - F2zz sbc (zz) -- - -- - -- - -- - C4zz CPY zz -- - CPY E4zz CPX zz -- - CPX C5zz CMP zz D5zz CMP zz,X E5zz SBC zz F5zz SBC zz,X C6zz DEC zz D6zz DEC zz,X E6zz INC zz F6zz INC zz,X -- - -- - -- - -- - C8 INY D8 CLD E8 INX F8 SED C9ii CMP #ii D9llhh CMP hhll,Y E9ii SBC #ii F9llhh SBC hhll,Y CA DEX DA phx EA NOP FA plx -- - -- - -- - -- - CCllhh CPY hhll -- - CPY ECllhh CPX hhll -- - CPX CDllhh CMP hhll DDllhh CMP hhll,X EDllhh SBC hhll FDllhh SBC hhll,X CEllhh DEC hhll DEllhh DEC hhll,X EEllhh INC hhll FEllhh INC hhll,X -- - -- - -- - -- - D2|DA|F2|FA in lowercase are 65C02 extensions C8: would be CPY A ; but is used for INY CA: would be DEC A ; but is used for DEX D4: would be CPY zz,X ; unused, missing for unknown reasons DC: would be CPX zz,X ; unused, missing for unknown reasons E8: would be CPX A ; but is used for INX EA: would be INC A ; but is used for NOP F4: would be CPY hhll,X ; unused, missing for unknown reasons FC: would be CPX hhll,X ; unused, missing for unknown reasons Instruction Code Table: ----------------------- (only opcodes, in order: ver: bit0..1/7..5, hor: bit4..2) (--- # are modify immediate, senseless, so this is no opcode) (--- ? denotes missing sensible instruction+addressmode combinations) ( ! denotes irregularity in instruction or adressmode placing) (xxx in lowercase are 65C02 extensions) + 00 04 08 0C 10 14 18 1C 00 BRK! tsb z PHP tsb hl BPL r trb z! CLC trb hl! 20 JSR hl! BIT z PLP BIT hl BMI r bit z,X? SEC bit hl,X? 40 RTI! --- ? PHA JMP hl BVC r --- ? CLI --- ? 60 RTS! stz!z? PLA JMP (hl) BVS r stz!z,X? SEI jmp (hl,X)? 80 bra r! STY z DEY! STY hl BCC r STY z,X TYA! stz!hl?! A0 LDY # LDY z TAY LDY hl BCS r LDY z,X CLV! LDY hl,X C0 CPY # CPY z INY! CPY hl BNE r --- ? CLD --- ? E0 CPX # CPX z INX! CPX hl BEQ r --- ? SED --- ? 01 ORA (,X) ORA z ORA # ORA hl ORA (),Y ORA z,X ORA hl,Y ORA hl,X 21 AND (,X) AND z AND # AND hl AND (),Y AND z,X AND hl,Y AND hl,X 41 EOR (,X) EOR z EOR # EOR hl EOR (),Y EOR z,X EOR hl,Y EOR hl,X 61 ADC (,X) ADC z ADC # ADC hl ADC (),Y ADC z,X ADC hl,Y ADC hl,X 81 STA (,X) STA z bit!# STA hl STA (),Y STA z,X STA hl,Y STA hl,X A1 LDA (,X) LDA z LDA # LDA hl LDA (),Y LDA z,X LDA hl,Y LDA hl,X C1 CMP (,X) CMP z CMP # CMP hl CMP (),Y CMP z,X CMP hl,Y CMP hl,X E1 SBC (,X) SBC z SBC # SBC hl SBC (),Y SBC z,X SBC hl,Y SBC hl,X 02 - ASL z ASL A ASL hl ora (z) ASL z,X inc A ASL hl,X 22 - ROL z ROL A ROL hl and (z) ROL z,X dec a ROL hl,X 42 - LSR z LSR A LSR hl eor (z) LSR z,X phy LSR hl,X 62 - ROR z ROR A ROR hl adc (z) ROR z,X ply ROR hl,X 82 --- # STX z TXA STX hl sta (z) STX z,Y TXS stz!hl,X?! A2 LDX # LDX z TAX LDX hl lda (z) LDX z,Y TSX LDX hl,Y C2 - DEC z DEX! DEC hl cmp (z) DEC z,X phx DEC hl,X E2 - INC z NOP! INC hl sbc (z) INC z,X plx INC hl,X 03 - - - - - - - - 23 - - - - - - - - 43 - - - - - - - - 63 - - - - - - - - 83 - - - - - - - - A3 - - - - - - - - C3 - - - - - - - - E3 - - - - - - - - (only opcodes, in order: ver: bit7..4/3, hor: bit2..0) (xxx in lowercase are 65C02 extensions) + 00 01 02 03 04 05 06 07 00 BRK ORA (,X) - - tsb z ORA z ASL z - 08 PHP ORA # ASL A - tsb hl ORA hl ASL hl - 10 BPL r ORA (),Y ora (z) - trb z ORA z,X ASL z,X - 18 CLC ORA hl,Y inc a - trb hl ORA hl,X ASL hl,X - 20 JSR hl AND (,X) - - BIT z AND z ROL z - 28 PLP AND # ROL A - BIT hl AND hl ROL hl - 30 BMI r AND (),Y and (z) - bit z,X AND z,X ROL z,X - 38 SEC AND hl,Y dec a - bit hl,X AND hl,X ROL hl,X - 40 RTI EOR (,X) - - - EOR z LSR z - 48 PHA EOR # LSR A - JMP hl EOR hl LSR hl - 50 BVC r EOR (),Y eor (z) - - EOR z,X LSR z,X - 58 CLI EOR hl,Y phy - - EOR hl,X LSR hl,X - 60 RTS ADC (,X) - - stz z ADC z ROR z - 68 PLA ADC # ROR A - JMP (hl) ADC hl ROR hl - 70 BVS r ADC (),Y adc (z) - stz z,X ADC z,X ROR z,X - 78 SEI ADC hl,Y ply - jmp (hlX)ADC hl,X ROR hl,X - 80 bra r STA (,X) - - STY z STA z STX z - 88 DEY bit # TXA - STY hl STA hl STX hl - 90 BCC r STA (),Y sta (z) - STY z,X STA z,X STX z,Y - 98 TYA STA hl,Y TXS - stz hl STA hl,X stz hl,X - A0 LDY # LDA (,X) LDX # - LDY z LDA z LDX z - A8 TAY LDA # TAX - LDY hl LDA hl LDX hl - B0 BCS r LDA (),Y lda (z) - LDY z,X LDA z,X LDX z,Y - B8 CLV LDA hl,Y TSX - LDY hl,X LDA hl,X LDX hl,Y - C0 CPY # CMP (,X) - - CPY z CMP z DEC z - C8 INY CMP # DEX - CPY hl CMP hl DEC hl - D0 BNE r CMP (),Y cmp (z) - - CMP z,X DEC z,X - D8 CLD CMP hl,Y phx - - CMP hl,X DEC hl,X - E0 CPX # SBC (,X) - - CPX z SBC z INC z - E8 INX SBC # NOP - CPX hl SBC hl INC hl - F0 BEQ r SBC (),Y sbc (z) - - SBC z,X INC z,X - F8 SED SBC hl,Y plx - - SBC hl,X INC hl,X -